With the advent of Ultra Large Scale Integrated (ULSI) technologies, the sizes of semiconductor devices and smaller than ever, which results in the packing density of a wafer being continuously increased. For example, this has caused a reduction in capacitor area, which in turn results in a reduction in cell capacitance. However, some problems occur due to the scaled down size of a device. For example, as the size of a capacitor decreases, the capacitance of the capacitor also decreases and the amount of the charge capable of being stored by the capacitor similarly decreases. This results in the capacitor being very susceptible to .alpha. particle interference and the charge held by the storage capacitor must be refreshed often.
Metal oxide semiconductor field effect transistors (MOSFETs) have been traditionally used and widely applied in the semiconductor technologies. As the trend of the integrated circuits, the fabrication of the MOSFET also meets various issues such as short channel effect. One of the issues is hot carriers that will inject into gate oxide, which is overcome by the development of the lightly doped drain (LDD) structure. Parasitic capacitance is a main reason to degrade the speed of the MOSFET, as it also causes high power for operating the devices. Typically, reasons to generate parasitic capacitance are the gate capacitance, gate-to-drain overlap capacitance, the junction capacitance and gate fringe capacitance.
The requirement of the ULSI technology is the need for devices capable of being operated at low supply voltage and having high speed. Thus, minimizing the parasitic capacitance is a key way to achieve high speed and low power devices for ULSI. See "Impact of Reduction of Gate to Drain Capacitance on Low Voltage Operated CMOS Devices, Kyoji Yamashita et al., 1995, Symposium on VLSI Technology Digest of Technical Papers.". Prior art approaches to overcoming these problems have resulted in the development of the gate-side air-gap (GAS) structure to reduce the parasitic capacitance in MOSFET. Please see "A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs, M. Togo et al., 1996, Symposium on VLSI Technology Digest of Technical Papers. High speed and low power operation devices are achieved by using the GAS structure in MOSFETs, which effectively reduces the gate fringe capacitance of the MOSFETs. However, it is difficult to reduce the valve of fringing field capacitance (C.sub.FR), due to the difficulty of scaling down the dielectric spacer thickness while scaling down the device dimension. The CRF becomes more important as the gate length is reduced to deep sub micron-meter range.